The present disclosure relates to a flash memory device and, more particularly, to a flash memory device and a program method capable of reducing program disturbance.
A non-volatile memory device may retain stored data in memory cells even when the power is turned off. As an example of such a non-volatile memory device, a flash memory device may have a function of electrically erasing data of memory cells collectively, so that it is widely used for applications such as computers, memory cards, and the like.
A flash memory device may be classified into a NOR type and a NAND type based upon the interconnection between memory cells and bit lines. In general, the NOR-type flash memory device is unfavorable for high integration, although it has an advantage that it can easily cope with high speed. The NAND-type flash memory device is favorable for high integration, because it consumes less current than the NOR-type flash memory device.
The NAND-type flash memory device may include a memory cell array as a region for storing information. The memory cell array may consist of a plurality of blocks, each of which has a plurality of cell strings (referred to as NAND strings). The NAND-type flash memory device may further include a page buffer circuit that is configured to store or read data in or from the memory cell array. As is known in the art, in the case of the NAND-type flash memory device, memory cells may be programmed or erased by use of the Fowler-Nordheim (FN) tunneling current. Erase and program methods of the NAND-type flash memory device are disclosed in greater detail in U.S. Pat. No. 5,473,563 entitled “Nonvolatile Semiconductor Memory” and in U.S. Pat. No. 5,696,717 entitled “Nonvolatile Integrated Circuit Memory Devices Having Adjustable Erase/Program Threshold Voltage Verification Capability”, the entire contents of which are hereby incorporated by reference.
The NAND-type flash memory device may be classified into a Single Level Cell (SLC) NAND-type flash memory device and a Multi Level Cell (MLC) NAND-type flash memory device.
The SLC NAND-type flash memory device can store 1-bit data per memory cell, while the MLC NAND-type flash memory device can store multi-bit data per memory cell.
FIG. 1 is a diagram showing threshold voltage distributions of a conventional MLC NAND-type flash memory device. The distribution figure indicates the case that 2-bit data is stored in each memory cell of the MLC NAND-type flash memory device. It will be understood by one of ordinary skill in the art, however, that the MLC NAND-type flash memory device is configured to store N-bit data (N is an integer of 3 or more) per memory cell.
Referring to FIG. 1, when erased, a memory cell may have an erase state ST0. Further, each memory cell may be programmed to have one of program states (or, data states) ST1, ST2 and ST3. Although not illustrated, in a case where 3-bit data is stored in each memory cell, each memory cell may have one of an erase state (ST0) and seven program states (ST1˜ST7).
A conventional NAND-type flash memory device may include a plurality of planes, each of which has a separate memory cell array. A memory cell array may include memory cells arranged in rows and columns. During a multi-plane program operation, the NAND-type flash memory device may perform a program operation with respect to all or selected planes at the same time. In this case, the NAND-type flash memory device may perform a verification operation for confirming whether a program operation of each plane is made in the normal fashion. A program operation is passed when data is programmed normally and is failed when data is not programmed normally. As is known in the art, the NAND-type flash memory device may repeat a program operation until the program operations all of the selected planes are passed.
Although a program-passed plane exists, the NAND-type flash memory device may perform a program operation with respect to all selected planes when at least one plane is judged to be program-failed. During the repeated program operation, a program voltage and a pass voltage are applied to all selected planes that consist of program-passed planes and program-failed planes. Accordingly, if the NAND-type flash memory device has at least one program-failed plane, the program and pass voltages may be applied to all selected planes that include program-passed planes.
In this case, memory cells in a program-passed plane may be unnecessarily supplied with the program and pass voltages. That is, memory cells in a program-passed plane may be unduly stressed. Memory cells thus stressed may be soft programmed, as illustrated by the broken lines in FIG. 1. This means that threshold voltages of the memory cells in the program-passed plane are increased, which is illustrated by the broken lines in FIG. 1. In other words, the memory cells in the program-passed plane may suffer from program disturbance.
A NAND-type flash memory device may read data from selected memory cells to output the read data externally. During a read operation, read voltages R0, R1, and R2 defined between ST0 and ST1, between ST2 and ST3, and between ST2 and ST3, respectively, may be used to read 2-bit data. If threshold voltage distributions of respective states are increased over the read voltages R0, R1, and R2, it is impossible to read data from memory cells having the states ST0, ST1, ST2, and ST3 accurately. That is, a read error may arise.
As a result, during a multi-plane program operation, if at least one plane is judged to be program-failed, the program and pass voltages may be continuously applied to memory cells of the program-passed planes. This may cause a read error due to program disturbance.